1. Field of the Invention
This invention relates generally to digital communication system decoders. More particularly, this invention relates to a radix-N architecture implemented with a joint de-interleaver/de-puncturer block. The radix-N architecture, which typically precedes a radix-N Viterbi decoder in a digital communication system, is scalable and requires less hardware than a conventional disjointed de-interleaver/de-puncturer architecture.
2. Description of the Prior Art
FIG. 1 illustrates a block diagram of a decoder 100 for a typical digital communication system. The main components of decoder 100 include de-interleaver 102, de-puncturer 104, Viterbi decoder 106, and descrambler 108. The port widths are shown for a 2×2 multi-input multi-output (MIMO) enabled system with 2^k-QAM, and an m-bit soft symbol for a Viterbi decoder having a 1/n rate code.
The symbol rate fsym for an orthogonal frequency division multiplexing (OFDM) system is defined as fsym=Ndata/Tburst, where Ndata is the number of OFDM tones per burst and Tburst is the burst duration. As an example, consider a MIMO enabled WLAN system with 108 Mb/s corresponding to k=6 (64-QAM), m=4 (4 soft information bits, design choice based on performance), n=4/3 (corresponding to 3/4 rate convolution code), fsym=12 MHz (symbol rate) and fbit=108 MHz (decoded bit rate). This particular system 200 is shown in FIG. 2.
Implementation of the forward error correction (FEC) blocks 102, 104 is dependant upon the decoded bit rate and clock frequency. If the clock frequency, for example, is 80 MHz, the port widths for one possible implementation 300 are shown in FIG. 3. This requires radix-4 implementation of de-puncturer 104 and Viterbi decoder 106.
To improve bit-error performance of the communication link, an interleaver in the transmitter and a de-interleaver in the receiver are employed. But, these data permutation operations are non-linear; and hence the address access pattern is irregular. Thus, the address pattern must be stored in a lookup table. A conventional de-interleaver and de-puncturer producing 1-bit per clock can be implemented as shown in FIG. 4 that shows a conventional de-interleaver block diagram 400, where the de-puncturer 104 needs to give an address increase signal to the de-interleaver controller 402 whenever the de-interleaved data is necessary. If a radix-4 de-interleaver and de-puncturer need to be implemented by employing FIG. 4 architecture, a 4-times higher clock speed must be used in the de-interleaver as shown in FIG. 5 (54 M samples/sec→216 M samples/sec) that shows a radix-4 de-interleaver and de-puncturer block diagram 500.
In view of the foregoing, it is both advantageous and desirable to provide a de-interleaver/de-puncturer architecture that is scalable and that is capable of achieving a higher data throughput than that achievable using a conventional disjointed de-interleaver/de-puncturer architecture. It would also be advantageous and desirable if the scalable de-interleaver/de-puncturer architecture were less complex than a conventional disjointed de-interleaver/de-puncturer architecture. It would further be advantageous and desirable if the scalable de-interleaver/de-puncturer architecture could achieve a higher data throughput without increasing the clock speed of the de-interleaver.